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verilog

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k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
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labs/lab3/impl/gwsynthesis/lab3.log Normal file
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GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
NOTE (EX0101) : Current top module is "mult2bit"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
GowinSynthesis finish