verilog
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54
labs/lab3/impl/temp/rtl_parser.result
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54
labs/lab3/impl/temp/rtl_parser.result
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[
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
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"InstLine" : 1,
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"InstName" : "fullAdder",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "fullAdder",
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"SubInsts" : [
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
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"InstLine" : 7,
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"InstName" : "h0",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfAdder"
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},
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
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"InstLine" : 8,
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"InstName" : "h1",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfAdder"
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}
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]
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},
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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"InstLine" : 1,
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"InstName" : "mult2bit",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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"ModuleLine" : 1,
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"ModuleName" : "mult2bit",
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"SubInsts" : [
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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"InstLine" : 14,
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"InstName" : "h0",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfAdder"
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},
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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"InstLine" : 15,
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"InstName" : "h1",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfAdder"
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}
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]
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}
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]
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