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verilog

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This commit is contained in:
k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
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13
labs/lab3_solution/adder3bit.v Normal file
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module adder3bit(
input [2:0] A,
input [2:0] B,
output [3:0] C
);
wire c1, c2, c3, c4;
ha a0(A[0], B[0], C[0], c1);
fa a1(A[1], B[1], c1, C[1], c2);
fa a2(A[2], B[2], c2, C[2], C[3]);
endmodule

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labs/lab3_solution/fa.v Normal file
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module fa(
input X, Y, Z,
output S, C
);
wire W0, W1, W2;
ha h0(X, Y, W0, W1);
ha h1(W0, Z, S, W2);
or(C, W1, W2);
endmodule

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labs/lab3_solution/ha.v Normal file
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module ha(
input X, Y,
output S, C
);
xor(S, X, Y);
and(C, X, Y);
endmodule

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labs/lab3_solution/run.sh Normal file
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iverilog *.v &&
vvp a.out &&
gtkwave dmp.vcd

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labs/lab3_solution/tb.v Normal file
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module tb();
reg [2:0] A, B;
wire [3:0] C;
adder3bit uut(A, B, C);
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
A = 3'd0; B = 3'd7; #10;
A = 3'd1; B = 3'd6; #10;
A = 3'd2; B = 3'd5; #10;
A = 3'd3; B = 3'd4; #10;
A = 3'd4; B = 3'd3; #10;
A = 3'd5; B = 3'd2; #10;
A = 3'd6; B = 3'd1; #10;
A = 3'd7; B = 3'd0; #10;
A = 3'd0; B = 3'd0; #10;
A = 3'd1; B = 3'd0; #10;
A = 3'd2; B = 3'd0; #10;
A = 3'd3; B = 3'd0; #10;
A = 3'd4; B = 3'd0; #10;
A = 3'd5; B = 3'd0; #10;
A = 3'd6; B = 3'd0; #10;
A = 3'd7; B = 3'd0; #10;
end
endmodule