156 lines
1.1 KiB
Plaintext
156 lines
1.1 KiB
Plaintext
$date
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Sat Jan 25 07:58:46 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module ayarliSayacTB $end
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$var wire 6 ! sayac [5:0] $end
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$var reg 1 " clk $end
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$var reg 1 # en $end
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$var reg 1 $ rst $end
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$var reg 3 % sayma_miktari [2:0] $end
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$var reg 1 & sayma_yonu $end
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$scope module uut $end
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$var wire 1 " clk $end
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$var wire 1 # en $end
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$var wire 1 $ rst $end
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$var wire 3 ' sayma_miktari [2:0] $end
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$var wire 1 & sayma_yonu $end
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$var reg 2 ( clk_divider [1:0] $end
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$var reg 3 ) miktar [2:0] $end
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$var reg 6 * sayac [5:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b0 *
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b1 )
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b1 (
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b110 '
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1&
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b110 %
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0$
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1#
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0"
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b0 !
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$end
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#1
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1"
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#2
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b10 (
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0"
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#3
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1"
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#4
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b11 (
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0"
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#5
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1"
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#6
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b1 !
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b1 *
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b110 )
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b0 (
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0"
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#7
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1"
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#8
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b1 (
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0"
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#9
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1"
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#10
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b10 (
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0"
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#11
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1"
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#12
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b11 (
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0"
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#13
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1"
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#14
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b111 !
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b111 *
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b0 (
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0"
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#15
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1"
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#16
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b1 (
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0"
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b10 %
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b10 '
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0#
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#17
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1"
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#18
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b10 (
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0"
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#19
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1"
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#20
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b11 (
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0"
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#21
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1"
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#22
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b0 (
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0"
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#23
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1"
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#24
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b1 (
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0"
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b11 %
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b11 '
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1#
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#25
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1"
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#26
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b10 (
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0"
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#27
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1"
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#28
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b11 (
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0"
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#29
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1"
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#30
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b1101 !
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b1101 *
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b11 )
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b0 (
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0"
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#31
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1"
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#32
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b0 !
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b0 *
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0"
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b10 %
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b10 '
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1$
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#33
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1"
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#34
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0"
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#35
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1"
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#36
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0"
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#37
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1"
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#38
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0"
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#39
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1"
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#40
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0"
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