RISC-V CORE

chapter5/RISCCore_0.2tb.v

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+module RISCCore_tb;
+  reg clk;
+  reg rst;
+  wire [31:0] pc;
+  wire [31:0] next_pc;
+  wire [31:0] instr;
+  
+  // Instantiate the RISC-V core
+  RISCCore uut (
+    .rst(rst),
+    .clk(clk),
+    .pc(pc),
+    .next_pc(next_pc),
+    .instr(instr)
+  );
+  
+  // Clock generation
+  always #5 clk = ~clk;
+  
+  // Test sequence
+  initial begin
+    // Initialize signals
+    clk = 0;
+    rst = 1;
+    
+    // Apply reset
+    #10 rst = 0;
+    
+    // Run for 100 clock cycles
+    #1000;
+    
+    // Display final register values
+    $display("\n=== Final Register Values ===");
+    for (integer i = 0; i < 32; i = i + 1) begin
+      if (uut.rf[i] != 0) begin
+        $display("x%d = %h", i, uut.rf[i]);
+      end
+    end
+    
+    // Display final memory contents
+    $display("\n=== Final Memory Contents ===");
+    for (integer i = 0; i < 32; i = i + 1) begin
+      if (uut.dmem[i] != 0) begin
+        $display("Mem[%d] = %h", i, uut.dmem[i]);
+      end
+    end
+    
+    $finish;
+  end
+  
+  // Monitor important signals
+  initial begin
+    $monitor("Time=%0t, PC=%h, Instr=%h", $time, pc, instr);
+  end
+endmodule