73 lines
2.0 KiB
Verilog
73 lines
2.0 KiB
Verilog
module pcIMemDec (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc,
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output wire [31:0] instr
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);
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//PC
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always @(posedge clk) begin
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if(rst) begin
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pc <= 32'h0;
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end
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else begin
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next_pc <= pc;
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pc <= pc + 32'h4;
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end
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end
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//IMem
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reg [31:0] imem [0:255];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]];
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//Decoder
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wire isUType = ((instr[6:0] == 7'b0110111) || (instr[6:0] == 7'b0010111));
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wire isIType = ((instr[6:0] == 7'b0000011) || (instr[6:0] == 7'b0000111) || (instr[6:0] == 7'b0010011) || (instr[6:0] == 7'b0011011) || (instr [6:0] == 7'b1100111));
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wire isRType = ((instr[6:0] == 7'b0101111) || (instr[6:0] == 7'b0110011) || (instr[6:0] == 7'b0111011) || (instr[6:0] == 7'b0110011));
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wire isSType = ((instr[6:0] == 7'b0100011) || (instr[6:0] == 7'b0100111));
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wire isBType = (instr[6:0] == 7'b1100011);
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wire isJType = (instr[6:0] == 7'b1101111);
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rd = instr[11:7];
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wire rs2Valid = (isRType || isSType || isBType);
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wire rs1Valid = (~isUType && ~isJType);
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wire rdValid = (~isSType && ~isBType);
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wire [3:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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wire funct3Valid = rs1Valid;
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wire funct7Valid = isRType;
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wire [31:0] Iimm = {{21{instr[31]}}, {instr[30:25]}, {instr[24:20]}};
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wire [31:0] Simm = {{21{instr[31]}}, {instr[30:25]}, {instr[11:7]}};
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wire [31:0] Bimm = {{20{instr[31]}}, {instr[7]}, {instr[30:25]}, {instr[11:8]}, 1'b0};
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wire [31:0] Uimm = {{instr[31]}, {instr[30:20]}, {instr[19:12]}, {12{1'b0}};
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wire [31:0] Jimm = {{12{instr[31]}}, {instr[19:12]}, {instr[20]}, {instr[30:25]}, {instr[24:21]}, 1'b0};
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//Instructions
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isBEQ = (funct3 == 000 && isBType);
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isBNE = (funct3 == 001 && isBType);
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isBLT = (funct3 == 100 && isBType);
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isBGE = (funct3 == 101 && isBType);
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isBLTU = (funct3 == 110 && isBType);
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isBGEU = (funct3 == 111 && isBType);
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isADDI = (funct3 == 000 && isIType);
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isADD = (funct7[5] == 0 && isRType);
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endmodule
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