23 lines
321 B
Verilog
23 lines
321 B
Verilog
module fibonacci (
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input clk,
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input rst,
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output reg [31:0] num
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);
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reg [31:0] nums [1:0];
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always @(posedge clk) begin
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if (rst) begin
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num <= 32'd1;
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nums[0] <= 32'd0;
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nums[1] <= 32'd0;
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end
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else begin
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nums[1] <= nums[0];
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nums[0] <= num;
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num <= nums[0] + nums[1];
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end
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end
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endmodule
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