newStep.v
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409
RTL/PROCESSOR/femtorv32_quark_bicycle.v
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409
RTL/PROCESSOR/femtorv32_quark_bicycle.v
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/*******************************************************************/
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// FemtoRV32, a collection of minimalistic RISC-V RV32 cores.
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// This version: The "Quark", the most elementary version of FemtoRV32.
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// A single VERILOG file, compact & understandable code.
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// (200 lines of code, 400 lines counting comments)
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//
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// Instruction set: RV32I + RDCYCLES
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//
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// Parameters:
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// Reset address can be defined using RESET_ADDR (default is 0).
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//
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// The ADDR_WIDTH parameter lets you define the width of the internal
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// address bus (and address computation logic).
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//
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// Macros:
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// optionally one may define NRV_IS_IO_ADDR(addr), that is supposed to:
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// evaluate to 1 if addr is in mapped IO space,
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// evaluate to 0 otherwise
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// (additional wait states are used when in IO space).
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// If left undefined, wait states are always used.
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//
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// NRV_COUNTER_WIDTH may be defined to reduce the number of bits used
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// by the ticks counter. If not defined, a 32-bits counter is generated.
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// (reducing its width may be useful for space-constrained designs).
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//
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// Bruno Levy, Matthias Koch, 2020-2021
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/*******************************************************************/
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// Firmware generation flags for this processor
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`define NRV_ARCH "rv32i"
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`define NRV_ABI "ilp32"
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`define NRV_OPTIMIZE "-Os"
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module FemtoRV32(
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input clk,
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output [31:0] mem_addr, // address bus
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output [31:0] mem_wdata, // data to be written
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output [3:0] mem_wmask, // write mask for the 4 bytes of each word
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input [31:0] mem_rdata, // input lines for both data and instr
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output mem_rstrb, // active to initiate memory read (used by IO)
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input mem_rbusy, // asserted if memory is busy reading value
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input mem_wbusy, // asserted if memory is busy writing value
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input reset // set to 0 to reset the processor
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);
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parameter RESET_ADDR = 32'h00000000;
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parameter ADDR_WIDTH = 24;
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/***************************************************************************/
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// Instruction decoding.
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/***************************************************************************/
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// Extracts rd,rs1,rs2,funct3,imm and opcode from instruction.
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// Reference: Table page 104 of:
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// https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// The destination register
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wire [4:0] rdId = instr[11:7];
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// The ALU function, decoded in 1-hot form (doing so reduces LUT count)
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// It is used as follows: funct3Is[val] <=> funct3 == val
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(* onehot *)
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wire [7:0] funct3Is = 8'b00000001 << instr[14:12];
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// The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12
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wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}};
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wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]};
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/* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder.
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wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]};
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wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
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wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
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/* verilator lint_on UNUSED */
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// Base RISC-V (RV32I) has only 10 different instructions !
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wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm]
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wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm
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wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm
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wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2
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wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2
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wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm
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wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm
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wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm
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wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm
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wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles
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wire isALU = isALUimm | isALUreg;
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/***************************************************************************/
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// The register file.
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/***************************************************************************/
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reg [31:0] rs1;
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reg [31:0] rs2;
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reg [31:0] registerFile [31:0];
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always @(posedge clk) begin
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if (writeBack)
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if (rdId != 0)
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registerFile[rdId] <= writeBackData;
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end
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/***************************************************************************/
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// The ALU. Does operations and tests combinatorially, except shifts.
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/***************************************************************************/
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// First ALU source, always rs1
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wire [31:0] aluIn1 = rs1;
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// Second ALU source, depends on opcode:
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// ALUreg, Branch: rs2
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// ALUimm, Load, JALR: Iimm
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wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm;
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// The adder is used by both arithmetic instructions and JALR.
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wire [31:0] aluPlus = aluIn1 + aluIn2;
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// Use a single 33 bits subtract to do subtraction and all comparisons
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// (trick borrowed from swapforth/J1)
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wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1;
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wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32];
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wire LTU = aluMinus[32];
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wire EQ = (aluMinus[31:0] == 0);
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/***************************************************************************/
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// Use the same shifter both for left and right shifts by
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// applying bit reversal
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wire [31:0] shifter_in = funct3Is[1] ?
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{aluIn1[ 0], aluIn1[ 1], aluIn1[ 2], aluIn1[ 3], aluIn1[ 4], aluIn1[ 5],
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aluIn1[ 6], aluIn1[ 7], aluIn1[ 8], aluIn1[ 9], aluIn1[10], aluIn1[11],
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aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17],
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aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23],
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aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29],
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aluIn1[30], aluIn1[31]} : aluIn1;
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/* verilator lint_off WIDTH */
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wire [31:0] shifter =
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$signed({instr[30] & aluIn1[31], shifter_in}) >>> aluIn2[4:0];
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/* verilator lint_on WIDTH */
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wire [31:0] leftshift = {
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shifter[ 0], shifter[ 1], shifter[ 2], shifter[ 3], shifter[ 4],
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shifter[ 5], shifter[ 6], shifter[ 7], shifter[ 8], shifter[ 9],
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shifter[10], shifter[11], shifter[12], shifter[13], shifter[14],
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shifter[15], shifter[16], shifter[17], shifter[18], shifter[19],
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shifter[20], shifter[21], shifter[22], shifter[23], shifter[24],
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shifter[25], shifter[26], shifter[27], shifter[28], shifter[29],
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shifter[30], shifter[31]};
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/***************************************************************************/
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// Notes:
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// - instr[30] is 1 for SUB and 0 for ADD
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// - for SUB, need to test also instr[5] to discriminate ADDI:
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// (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !)
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// - instr[30] is 1 for SRA (do sign extension) and 0 for SRL
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wire [31:0] aluOut =
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(funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) |
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(funct3Is[1] ? leftshift : 32'b0) |
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(funct3Is[2] ? {31'b0, LT} : 32'b0) |
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(funct3Is[3] ? {31'b0, LTU} : 32'b0) |
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(funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) |
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(funct3Is[5] ? shifter : 32'b0) |
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(funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) |
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(funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) ;
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/***************************************************************************/
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// The predicate for conditional branches.
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/***************************************************************************/
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wire predicate =
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funct3Is[0] & EQ | // BEQ
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funct3Is[1] & !EQ | // BNE
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funct3Is[4] & LT | // BLT
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funct3Is[5] & !LT | // BGE
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funct3Is[6] & LTU | // BLTU
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funct3Is[7] & !LTU ; // BGEU
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/***************************************************************************/
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// Program counter and branch target computation.
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/***************************************************************************/
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reg [ADDR_WIDTH-1:0] PC; // The program counter.
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reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are
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// ignored (not used in RV32I base instr set).
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wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4;
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// An adder used to compute branch address, JAL address and AUIPC.
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// branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm
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// Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm)
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wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] :
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instr[4] ? Uimm[ADDR_WIDTH-1:0] :
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Bimm[ADDR_WIDTH-1:0] );
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// A separate adder to compute the destination of load/store.
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// testing instr[5] is equivalent to testing isStore in this context.
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wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] +
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(instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]);
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/* verilator lint_off WIDTH */
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// internal address registers and cycles counter may have less than
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// 32 bits, so we deactivate width test for mem_addr and writeBackData
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wire [ADDR_WIDTH-1:0] PC_new =
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isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} :
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jumpToPCplusImm ? PCplusImm :
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PCplus4;
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assign mem_addr = state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ? PC :
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state[EXECUTE_bit] & ~isLoad & ~isStore ? PC_new :
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loadstore_addr ;
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/***************************************************************************/
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// The value written back to the register file.
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/***************************************************************************/
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wire [31:0] writeBackData =
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(isSYSTEM ? cycles : 32'b0) | // SYSTEM
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(isLUI ? Uimm : 32'b0) | // LUI
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(isALU ? aluOut : 32'b0) | // ALUreg, ALUimm
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(isAUIPC ? PCplusImm : 32'b0) | // AUIPC
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(isJALR | isJAL ? PCplus4 : 32'b0) | // JAL, JALR
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(isLoad ? LOAD_data : 32'b0) ; // Load
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/* verilator lint_on WIDTH */
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/***************************************************************************/
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// LOAD/STORE
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/***************************************************************************/
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// All memory accesses are aligned on 32 bits boundary. For this
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// reason, we need some circuitry that does unaligned halfword
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// and byte load/store, based on:
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// - funct3[1:0]: 00->byte 01->halfword 10->word
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// - mem_addr[1:0]: indicates which byte/halfword is accessed
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wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00;
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wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01;
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// LOAD, in addition to funct3[1:0], LOAD depends on:
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// - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion
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wire LOAD_sign =
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!instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]);
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wire [31:0] LOAD_data =
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mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} :
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mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} :
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mem_rdata ;
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wire [15:0] LOAD_halfword =
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loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0];
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wire [7:0] LOAD_byte =
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loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0];
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// STORE
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assign mem_wdata[ 7: 0] = rs2[7:0];
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assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8];
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assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16];
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assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] :
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loadstore_addr[1] ? rs2[15:8] : rs2[31:24];
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// The memory write mask:
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// 1111 if writing a word
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// 0011 or 1100 if writing a halfword
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// (depending on loadstore_addr[1])
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// 0001, 0010, 0100 or 1000 if writing a byte
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// (depending on loadstore_addr[1:0])
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wire [3:0] STORE_wmask =
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mem_byteAccess ?
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(loadstore_addr[1] ?
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(loadstore_addr[0] ? 4'b1000 : 4'b0100) :
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(loadstore_addr[0] ? 4'b0010 : 4'b0001)
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) :
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mem_halfwordAccess ?
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(loadstore_addr[1] ? 4'b1100 : 4'b0011) :
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4'b1111;
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/*************************************************************************/
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// And, last but not least, the state machine.
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/*************************************************************************/
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localparam FETCH_INSTR_bit = 0;
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localparam WAIT_INSTR_bit = 1;
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localparam EXECUTE_bit = 2;
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localparam WAIT_ALU_OR_MEM_bit = 3;
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localparam NB_STATES = 4;
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localparam FETCH_INSTR = 1 << FETCH_INSTR_bit;
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localparam WAIT_INSTR = 1 << WAIT_INSTR_bit;
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localparam EXECUTE = 1 << EXECUTE_bit;
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localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit;
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(* onehot *)
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reg [NB_STATES-1:0] state;
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// The signals (internal and external) that are determined
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// combinatorially from state and other signals.
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// register write-back enable.
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wire writeBack = ~(isBranch | isStore ) &
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(state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]);
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// The memory-read signal.
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assign mem_rstrb = state[EXECUTE_bit] & ~isStore | state[FETCH_INSTR_bit];
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// The mask for memory-write.
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assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask;
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wire jumpToPCplusImm = isJAL | (isBranch & predicate);
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`ifdef NRV_IS_IO_ADDR
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wire needToWait = isLoad |
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isStore & `NRV_IS_IO_ADDR(mem_addr) ;
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`else
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||||
wire needToWait = isLoad | isStore ;
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||||
`endif
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||||
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always @(posedge clk) begin
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||||
if(!reset) begin
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||||
state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy
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||||
PC <= RESET_ADDR[ADDR_WIDTH-1:0];
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||||
end else
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||||
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// See note [1] at the end of this file.
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||||
(* parallel_case *)
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||||
case(1'b1)
|
||||
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state[WAIT_INSTR_bit]: begin
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if(!mem_rbusy) begin // may be high when executing from SPI flash
|
||||
rs1 <= registerFile[mem_rdata[19:15]];
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||||
rs2 <= registerFile[mem_rdata[24:20]];
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instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see
|
||||
state <= EXECUTE; // also the declaration of instr).
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||||
end
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||||
end
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state[EXECUTE_bit]: begin
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||||
PC <= PC_new;
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state <= needToWait ? WAIT_ALU_OR_MEM : WAIT_INSTR;
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||||
end
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||||
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state[WAIT_ALU_OR_MEM_bit]: begin
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if(!mem_rbusy & !mem_wbusy) state <= FETCH_INSTR;
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end
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default: begin // FETCH_INSTR
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state <= WAIT_INSTR;
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||||
end
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||||
|
||||
endcase
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||||
end
|
||||
|
||||
/***************************************************************************/
|
||||
// Cycle counter
|
||||
/***************************************************************************/
|
||||
|
||||
`ifdef NRV_COUNTER_WIDTH
|
||||
reg [`NRV_COUNTER_WIDTH-1:0] cycles;
|
||||
`else
|
||||
reg [31:0] cycles;
|
||||
`endif
|
||||
always @(posedge clk) cycles <= cycles + 1;
|
||||
|
||||
`ifdef BENCH
|
||||
initial begin
|
||||
cycles = 0;
|
||||
registerFile[0] = 0;
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
/*****************************************************************************/
|
||||
// Notes:
|
||||
//
|
||||
// [1] About the "reverse case" statement, also used in Claire Wolf's picorv32:
|
||||
// It is just a cleaner way of writing a series of cascaded if() statements,
|
||||
// To understand it, think about the case statement *in general* as follows:
|
||||
// case (expr)
|
||||
// val_1: statement_1
|
||||
// val_2: statement_2
|
||||
// ... val_n: statement_n
|
||||
// endcase
|
||||
// The first statement_i such that expr == val_i is executed.
|
||||
// Now if expr is 1'b1:
|
||||
// case (1'b1)
|
||||
// cond_1: statement_1
|
||||
// cond_2: statement_2
|
||||
// ... cond_n: statement_n
|
||||
// endcase
|
||||
// It is *exactly the same thing*, the first statement_i such that
|
||||
// expr == cond_i is executed (that is, such that 1'b1 == cond_i,
|
||||
// in other words, such that cond_i is true)
|
||||
// More on this:
|
||||
// https://stackoverflow.com/questions/15418636/case-statement-in-verilog
|
||||
//
|
||||
// [2] state uses 1-hot encoding (at any time, state has only one bit set to 1).
|
||||
// It uses a larger number of bits (one bit per state), but often results in
|
||||
// a both more compact (fewer LUTs) and faster state machine.
|
||||
|
||||
Reference in New Issue
Block a user