newStep.v
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211
step7.v
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211
step7.v
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/**
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* Step 7: Creating a RISC-V processor
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* Assembly
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* DONE*
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*/
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`default_nettype none
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`include "clockworks.v"
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module SOC (
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input CLK, // system clock
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input RESET, // reset button
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output [4:0] LEDS, // system LEDs
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input RXD, // UART receive
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output TXD // UART transmit
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);
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wire clk; // internal clock
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wire resetn; // internal reset signal, goes low on reset
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// Plug the leds on register 1 to see its contents
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reg [4:0] leds;
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assign LEDS = leds;
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reg [31:0] MEM [0:255];
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reg [31:0] PC; // program counter
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reg [31:0] instr; // current instruction
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`include "riscv_assembly.v"
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initial begin
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PC = 0;
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ADD(x0,x0,x0);
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ADD(x1,x0,x0);
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ADDI(x1,x1,1);
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ADDI(x1,x1,1);
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ADDI(x1,x1,1);
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ADDI(x1,x1,1);
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ADD(x2,x1,x0);
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ADD(x3,x1,x2);
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SRLI(x3,x3,3);
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SLLI(x3,x3,31);
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SRAI(x3,x3,5);
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SRLI(x1,x3,26);
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EBREAK();
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end
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// See the table P. 105 in RISC-V manual
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// The 10 RISC-V instructions
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wire isALUreg = (instr[6:0] == 7'b0110011); // rd <- rs1 OP rs2
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wire isALUimm = (instr[6:0] == 7'b0010011); // rd <- rs1 OP Iimm
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wire isBranch = (instr[6:0] == 7'b1100011); // if(rs1 OP rs2) PC<-PC+Bimm
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wire isJALR = (instr[6:0] == 7'b1100111); // rd <- PC+4; PC<-rs1+Iimm
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wire isJAL = (instr[6:0] == 7'b1101111); // rd <- PC+4; PC<-PC+Jimm
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wire isAUIPC = (instr[6:0] == 7'b0010111); // rd <- PC + Uimm
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wire isLUI = (instr[6:0] == 7'b0110111); // rd <- Uimm
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wire isLoad = (instr[6:0] == 7'b0000011); // rd <- mem[rs1+Iimm]
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wire isStore = (instr[6:0] == 7'b0100011); // mem[rs1+Simm] <- rs2
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wire isSYSTEM = (instr[6:0] == 7'b1110011); // special
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// The 5 immediate formats
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wire [31:0] Uimm={ instr[31], instr[30:12], {12{1'b0}}};
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wire [31:0] Iimm={{21{instr[31]}}, instr[30:20]};
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wire [31:0] Simm={{21{instr[31]}}, instr[30:25],instr[11:7]};
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wire [31:0] Bimm={{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
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wire [31:0] Jimm={{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
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// Source and destination registers
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wire [4:0] rs1Id = instr[19:15];
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wire [4:0] rs2Id = instr[24:20];
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wire [4:0] rdId = instr[11:7];
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// function codes
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wire [2:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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// The registers bank
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reg [31:0] RegisterBank [0:31];
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reg [31:0] rs1; // value of source
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reg [31:0] rs2; // registers.
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wire [31:0] writeBackData; // data to be written to rd
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wire writeBackEn; // asserted if data should be written to rd
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`ifdef BENCH
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integer i;
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initial begin
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for(i=0; i<32; ++i) begin
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RegisterBank[i] = 0;
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end
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end
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`endif
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// The ALU
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wire [31:0] aluIn1 = rs1;
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wire [31:0] aluIn2 = isALUreg ? rs2 : Iimm;
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reg [31:0] aluOut;
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wire [4:0] shamt = isALUreg ? rs2[4:0] : instr[24:20]; // shift amount
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// ADD/SUB/ADDI:
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// funct7[5] is 1 for SUB and 0 for ADD. We need also to test instr[5]
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// to make the difference with ADDI
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//
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// SRLI/SRAI/SRL/SRA:
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// funct7[5] is 1 for arithmetic shift (SRA/SRAI) and
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// 0 for logical shift (SRL/SRLI)
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always @(*) begin
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case(funct3)
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3'b000: aluOut = (funct7[5] & instr[5]) ?
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(aluIn1 - aluIn2) : (aluIn1 + aluIn2);
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3'b001: aluOut = aluIn1 << shamt;
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3'b010: aluOut = ($signed(aluIn1) < $signed(aluIn2));
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3'b011: aluOut = (aluIn1 < aluIn2);
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3'b100: aluOut = (aluIn1 ^ aluIn2);
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3'b101: aluOut = funct7[5]? ($signed(aluIn1) >>> shamt) :
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($signed(aluIn1) >> shamt);
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3'b110: aluOut = (aluIn1 | aluIn2);
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3'b111: aluOut = (aluIn1 & aluIn2);
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endcase
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end
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// The state machine
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localparam FETCH_INSTR = 0;
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localparam FETCH_REGS = 1;
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localparam EXECUTE = 2;
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reg [1:0] state = FETCH_INSTR;
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// register write back
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assign writeBackData = aluOut;
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assign writeBackEn = (state == EXECUTE && (isALUreg || isALUimm));
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always @(posedge clk) begin
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if(!resetn) begin
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PC <= 0;
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state <= FETCH_INSTR;
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end else begin
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if(writeBackEn && rdId != 0) begin
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RegisterBank[rdId] <= writeBackData;
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// For displaying what happens.
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if(rdId == 1) begin
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leds <= writeBackData;
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end
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`ifdef BENCH
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$display("x%0d <= %b",rdId,writeBackData);
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`endif
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end
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case(state)
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FETCH_INSTR: begin
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instr <= MEM[PC[31:2]];
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state <= FETCH_REGS;
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end
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FETCH_REGS: begin
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rs1 <= RegisterBank[rs1Id];
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rs2 <= RegisterBank[rs2Id];
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state <= EXECUTE;
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end
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EXECUTE: begin
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if(!isSYSTEM) begin
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PC <= PC + 4;
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end
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state <= FETCH_INSTR;
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`ifdef BENCH
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if(isSYSTEM) $finish();
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`endif
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end
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endcase
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end
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end
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`ifdef BENCH
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always @(posedge clk) begin
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if(state == FETCH_REGS) begin
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case (1'b1)
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isALUreg: $display(
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"ALUreg rd=%d rs1=%d rs2=%d funct3=%b",
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rdId, rs1Id, rs2Id, funct3
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);
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isALUimm: $display(
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"ALUimm rd=%d rs1=%d imm=%0d funct3=%b",
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rdId, rs1Id, Iimm, funct3
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);
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isBranch: $display("BRANCH");
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isJAL: $display("JAL");
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isJALR: $display("JALR");
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isAUIPC: $display("AUIPC");
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isLUI: $display("LUI");
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isLoad: $display("LOAD");
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isStore: $display("STORE");
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isSYSTEM: $display("SYSTEM");
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endcase
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if(isSYSTEM) begin
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$finish();
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end
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end
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end
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`endif
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// Gearbox and reset circuitry.
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Clockworks #(
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.SLOW(19) // Divide clock frequency by 2^19
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)CW(
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.CLK(CLK),
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.RESET(RESET),
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.clk(clk),
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.resetn(resetn)
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);
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assign TXD = 1'b0; // not used for now
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endmodule
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