41 lines
1013 B
Verilog
41 lines
1013 B
Verilog
// femtorv32, a minimalistic RISC-V RV32I core
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// Bruno Levy, 2020-2021
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//
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// This file: driver for SDCard (does nearly nothing,
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// for now it is just an interface for software bitbanging,
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// see FIRMWARE/LIBFEMTORV32/spi_sd.c)
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//
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module SDCard(
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input wire clk, // system clock
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input wire rstrb, // read strobe
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input wire wstrb, // write strobe
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input wire sel, // select (read/write ignored if low)
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input wire [31:0] wdata, // data to be written
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output wire [31:0] rdata, // read data
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output wire MOSI,
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input wire MISO,
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output wire CS_N,
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output wire CLK
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);
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reg [2:0] state; // CS_N,CLK,MOSI
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assign CS_N = state[2];
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assign CLK = state[1];
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assign MOSI = state[0];
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initial begin
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state = 3'b100;
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end
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assign rdata = (sel ? {31'b0, MISO} : 32'b0);
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always @(posedge clk) begin
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if(sel && wstrb) begin
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state <= wdata[2:0];
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end
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end
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endmodule
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