212 lines
4.9 KiB
Verilog
212 lines
4.9 KiB
Verilog
/*
|
|
* Do not edit this file, it was generated by gen_pll.sh
|
|
*
|
|
* FPGA kind : GOWIN
|
|
* Input frequency: 27 MHz
|
|
*/
|
|
|
|
module femtoPLL #(
|
|
parameter freq = 40
|
|
) (
|
|
input wire pclk,
|
|
output wire clk
|
|
);
|
|
rPLL pll_i(
|
|
.CLKOUTP(),
|
|
.CLKOUTD(),
|
|
.CLKOUTD3(),
|
|
.RESET(1'b0),
|
|
.RESET_P(1'b0),
|
|
.CLKFB(1'b0),
|
|
.FBDSEL(6'b0),
|
|
.IDSEL(6'b0),
|
|
.ODSEL(6'b0),
|
|
.PSDA(4'b0),
|
|
.DUTYDA(4'b0),
|
|
.FDLY(4'b0),
|
|
.CLKIN(pclk),
|
|
.CLKOUT(clk)
|
|
);
|
|
defparam pll_i.FCLKIN="27";
|
|
generate
|
|
case(freq)
|
|
16: begin
|
|
defparam pll_i.IDIV_SEL=4;
|
|
defparam pll_i.FBDIV_SEL=2;
|
|
defparam pll_i.ODIV_SEL=32;
|
|
end
|
|
20: begin
|
|
defparam pll_i.IDIV_SEL=3;
|
|
defparam pll_i.FBDIV_SEL=2;
|
|
defparam pll_i.ODIV_SEL=32;
|
|
end
|
|
24: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=7;
|
|
defparam pll_i.ODIV_SEL=32;
|
|
end
|
|
25: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=7;
|
|
defparam pll_i.ODIV_SEL=32;
|
|
end
|
|
30: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=9;
|
|
defparam pll_i.ODIV_SEL=16;
|
|
end
|
|
35: begin
|
|
defparam pll_i.IDIV_SEL=6;
|
|
defparam pll_i.FBDIV_SEL=8;
|
|
defparam pll_i.ODIV_SEL=16;
|
|
end
|
|
40: begin
|
|
defparam pll_i.IDIV_SEL=1;
|
|
defparam pll_i.FBDIV_SEL=2;
|
|
defparam pll_i.ODIV_SEL=16;
|
|
end
|
|
45: begin
|
|
defparam pll_i.IDIV_SEL=2;
|
|
defparam pll_i.FBDIV_SEL=4;
|
|
defparam pll_i.ODIV_SEL=16;
|
|
end
|
|
48: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=15;
|
|
defparam pll_i.ODIV_SEL=16;
|
|
end
|
|
50: begin
|
|
defparam pll_i.IDIV_SEL=6;
|
|
defparam pll_i.FBDIV_SEL=12;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
55: begin
|
|
defparam pll_i.IDIV_SEL=0;
|
|
defparam pll_i.FBDIV_SEL=1;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
60: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=19;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
65: begin
|
|
defparam pll_i.IDIV_SEL=4;
|
|
defparam pll_i.FBDIV_SEL=11;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
66: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=21;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
70: begin
|
|
defparam pll_i.IDIV_SEL=4;
|
|
defparam pll_i.FBDIV_SEL=12;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
75: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=24;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
80: begin
|
|
defparam pll_i.IDIV_SEL=0;
|
|
defparam pll_i.FBDIV_SEL=2;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
85: begin
|
|
defparam pll_i.IDIV_SEL=6;
|
|
defparam pll_i.FBDIV_SEL=21;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
90: begin
|
|
defparam pll_i.IDIV_SEL=2;
|
|
defparam pll_i.FBDIV_SEL=9;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
95: begin
|
|
defparam pll_i.IDIV_SEL=1;
|
|
defparam pll_i.FBDIV_SEL=6;
|
|
defparam pll_i.ODIV_SEL=8;
|
|
end
|
|
100: begin
|
|
defparam pll_i.IDIV_SEL=6;
|
|
defparam pll_i.FBDIV_SEL=25;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
105: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=34;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
110: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=36;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
115: begin
|
|
defparam pll_i.IDIV_SEL=3;
|
|
defparam pll_i.FBDIV_SEL=16;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
120: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=39;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
125: begin
|
|
defparam pll_i.IDIV_SEL=7;
|
|
defparam pll_i.FBDIV_SEL=36;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
130: begin
|
|
defparam pll_i.IDIV_SEL=4;
|
|
defparam pll_i.FBDIV_SEL=23;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
135: begin
|
|
defparam pll_i.IDIV_SEL=0;
|
|
defparam pll_i.FBDIV_SEL=4;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
140: begin
|
|
defparam pll_i.IDIV_SEL=4;
|
|
defparam pll_i.FBDIV_SEL=25;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
150: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=49;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
160: begin
|
|
defparam pll_i.IDIV_SEL=8;
|
|
defparam pll_i.FBDIV_SEL=52;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
170: begin
|
|
defparam pll_i.IDIV_SEL=6;
|
|
defparam pll_i.FBDIV_SEL=43;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
180: begin
|
|
defparam pll_i.IDIV_SEL=2;
|
|
defparam pll_i.FBDIV_SEL=19;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
190: begin
|
|
defparam pll_i.IDIV_SEL=0;
|
|
defparam pll_i.FBDIV_SEL=6;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
200: begin
|
|
defparam pll_i.IDIV_SEL=4;
|
|
defparam pll_i.FBDIV_SEL=36;
|
|
defparam pll_i.ODIV_SEL=4;
|
|
end
|
|
default: UNKNOWN_FREQUENCY unknown_frequency();
|
|
endcase
|
|
endgenerate
|
|
endmodule
|