306 lines
12 KiB
Verilog
306 lines
12 KiB
Verilog
// Special version of femtosoc for mecrisp-quintus (Forth interpreter) on IceStick, by Matthias Koch
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// mecrisp website: http://mecrisp.sourceforge.net/
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`default_nettype none // Makes it easier to detect typos !
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`define NRV_MINIRV32 // Mini config, can execute code stored in SPI flash from 1Mb offset (mapped to address 0x800000)
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`define NRV_RUN_FROM_SPI_FLASH // Running code from the SPI flash (changes the constant for delay loops)
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`define NRV_RESET_ADDR 24'h810000 // Directly jump into mapped SPI Flash,
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`define NRV_COUNTER_WIDTH 32 // Number of bits in click counter
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`include "PROCESSOR/femtorv32_quark.v" // Minimalistic version of the processor
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`include "DEVICES/uart_picosoc_shrunk.v"
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`include "DEVICES/MappedSPIFlash.v"
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module femtosoc(
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input oscillator,
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output D1, D2, D3, D4, D5,
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output TXD,
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input RXD,
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output spi_clk,
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output spi_cs_n,
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inout spi_mosi,
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inout spi_miso,
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// input IR_RX,
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// output IR_TX,
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// output IR_SD,
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inout PIO1_02, // PMOD 1
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inout PIO1_03, // PMOD 2
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inout PIO1_04, // PMOD 3
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inout PIO1_05, // PMOD 4
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inout PIO1_06, // PMOD 5
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inout PIO1_07, // PMOD 6
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inout PIO1_08, // PMOD 7
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inout PIO1_09, // PMOD 8
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inout PIO0_02, // Header 1
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inout PIO0_03, // Header 2
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inout PIO0_04, // Header 3
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inout PIO0_05, // Header 4
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inout PIO0_06, // Header 5
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inout PIO0_07, // Header 6
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inout PIO0_08, // Header 7
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inout PIO0_09, // Header 8
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inout PIO2_10, // Header 1
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inout PIO2_11, // Header 2
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inout PIO2_12, // Header 3
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inout PIO2_13, // Header 4
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inout PIO2_14, // Header 5
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inout PIO2_15, // Header 6
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inout PIO2_16, // Header 7
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inout PIO2_17, // Header 8
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input reset_button
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);
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// ###### Clock #########################################
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wire clk; // Configured for 48 MHz
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SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
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.PLLOUT_SELECT("GENCLK"),
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.DIVR(4'b0000),
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.DIVF(7'b0111111),
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.DIVQ(3'b100),
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.FILTER_RANGE(3'b001),
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) uut (
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.REFERENCECLK(oscillator),
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.PLLOUTCORE(clk),
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.RESETB(1'b1),
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.BYPASS(1'b0)
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);
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// ###### Reset logic ###################################
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reg [7:0] reset_cnt = 0;
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wire resetq = &reset_cnt;
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always @(posedge clk, negedge reset_button) begin
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if (!reset_button) reset_cnt <= 0;
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else reset_cnt <= reset_cnt + !resetq;
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end
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// ###### Cycle counter #################################
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//reg [31:0] cycles;
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//always @(posedge clk) cycles <= cycles + 1;
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// ###### LEDS ##########################################
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reg [4:0] LEDs;
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assign {D5,D4,D3,D2,D1} = LEDs;
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// ###### RING OSCILLATOR ###############################
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wire [1:0] buffers_in, buffers_out;
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assign buffers_in = {buffers_out[0:0], ~buffers_out[1]};
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SB_LUT4 #(
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.LUT_INIT(16'd2)
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) buffers [1:0] (
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.O(buffers_out),
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.I0(buffers_in),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0)
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);
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wire random = ~buffers_out[1];
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// ###### GPIO ##########################################
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wire [24:0] port_in;
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reg [23:0] port_out;
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reg [23:0] port_dir;
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assign port_in[24] = random;
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// PMOD
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio0 (.PACKAGE_PIN(PIO1_02), .D_OUT_0(port_out[ 0]), .D_IN_0(port_in[ 0]), .OUTPUT_ENABLE(port_dir[ 0]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio1 (.PACKAGE_PIN(PIO1_03), .D_OUT_0(port_out[ 1]), .D_IN_0(port_in[ 1]), .OUTPUT_ENABLE(port_dir[ 1]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio2 (.PACKAGE_PIN(PIO1_04), .D_OUT_0(port_out[ 2]), .D_IN_0(port_in[ 2]), .OUTPUT_ENABLE(port_dir[ 2]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio3 (.PACKAGE_PIN(PIO1_05), .D_OUT_0(port_out[ 3]), .D_IN_0(port_in[ 3]), .OUTPUT_ENABLE(port_dir[ 3]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio4 (.PACKAGE_PIN(PIO1_06), .D_OUT_0(port_out[ 4]), .D_IN_0(port_in[ 4]), .OUTPUT_ENABLE(port_dir[ 4]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio5 (.PACKAGE_PIN(PIO1_07), .D_OUT_0(port_out[ 5]), .D_IN_0(port_in[ 5]), .OUTPUT_ENABLE(port_dir[ 5]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio6 (.PACKAGE_PIN(PIO1_08), .D_OUT_0(port_out[ 6]), .D_IN_0(port_in[ 6]), .OUTPUT_ENABLE(port_dir[ 6]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) fio7 (.PACKAGE_PIN(PIO1_09), .D_OUT_0(port_out[ 7]), .D_IN_0(port_in[ 7]), .OUTPUT_ENABLE(port_dir[ 7]));
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// Header 1
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio0 (.PACKAGE_PIN(PIO0_02), .D_OUT_0(port_out[ 8]), .D_IN_0(port_in[ 8]), .OUTPUT_ENABLE(port_dir[ 8]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio1 (.PACKAGE_PIN(PIO0_03), .D_OUT_0(port_out[ 9]), .D_IN_0(port_in[ 9]), .OUTPUT_ENABLE(port_dir[ 9]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio2 (.PACKAGE_PIN(PIO0_04), .D_OUT_0(port_out[10]), .D_IN_0(port_in[10]), .OUTPUT_ENABLE(port_dir[10]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio3 (.PACKAGE_PIN(PIO0_05), .D_OUT_0(port_out[11]), .D_IN_0(port_in[11]), .OUTPUT_ENABLE(port_dir[11]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio4 (.PACKAGE_PIN(PIO0_06), .D_OUT_0(port_out[12]), .D_IN_0(port_in[12]), .OUTPUT_ENABLE(port_dir[12]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio5 (.PACKAGE_PIN(PIO0_07), .D_OUT_0(port_out[13]), .D_IN_0(port_in[13]), .OUTPUT_ENABLE(port_dir[13]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio6 (.PACKAGE_PIN(PIO0_08), .D_OUT_0(port_out[14]), .D_IN_0(port_in[14]), .OUTPUT_ENABLE(port_dir[14]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) gio7 (.PACKAGE_PIN(PIO0_09), .D_OUT_0(port_out[15]), .D_IN_0(port_in[15]), .OUTPUT_ENABLE(port_dir[15]));
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// Header 2
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio0 (.PACKAGE_PIN(PIO2_10), .D_OUT_0(port_out[16]), .D_IN_0(port_in[16]), .OUTPUT_ENABLE(port_dir[16]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio1 (.PACKAGE_PIN(PIO2_11), .D_OUT_0(port_out[17]), .D_IN_0(port_in[17]), .OUTPUT_ENABLE(port_dir[17]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio2 (.PACKAGE_PIN(PIO2_12), .D_OUT_0(port_out[18]), .D_IN_0(port_in[18]), .OUTPUT_ENABLE(port_dir[18]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio3 (.PACKAGE_PIN(PIO2_13), .D_OUT_0(port_out[19]), .D_IN_0(port_in[19]), .OUTPUT_ENABLE(port_dir[19]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio4 (.PACKAGE_PIN(PIO2_14), .D_OUT_0(port_out[20]), .D_IN_0(port_in[20]), .OUTPUT_ENABLE(port_dir[20]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio5 (.PACKAGE_PIN(PIO2_15), .D_OUT_0(port_out[21]), .D_IN_0(port_in[21]), .OUTPUT_ENABLE(port_dir[21]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio6 (.PACKAGE_PIN(PIO2_16), .D_OUT_0(port_out[22]), .D_IN_0(port_in[22]), .OUTPUT_ENABLE(port_dir[22]));
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SB_IO #(.PIN_TYPE(6'b1010_01)) hio7 (.PACKAGE_PIN(PIO2_17), .D_OUT_0(port_out[23]), .D_IN_0(port_in[23]), .OUTPUT_ENABLE(port_dir[23]));
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// ###### UART ##########################################
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wire serial_valid, serial_busy;
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wire [7:0] serial_data;
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wire serial_wr = io_wstrb & io_word_address[IO_UART_DAT_bit];
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wire serial_rd = io_rstrb & io_word_address[IO_UART_DAT_bit];
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buart #(
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.FREQ_MHZ(48),
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.BAUDS(115200)
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) the_buart (
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.clk(clk),
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.resetq(resetq),
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.rx(RXD),
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.tx(TXD),
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.rd(serial_rd),
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.wr(serial_wr),
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.valid(serial_valid),
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.busy(serial_busy),
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.tx_data(io_wdata[7:0]),
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.rx_data(serial_data)
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);
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// ###### IO PORTS ######################################
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// We got a total of 20 bits for 1-hot addressing of IO registers.
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localparam IO_LEDS_bit = 0; // RW four leds
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localparam IO_UART_DAT_bit = 1; // RW write: data to send (8 bits) read: received data (8 bits)
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localparam IO_UART_CNTL_bit = 2; // R status. bit 8: valid read data. bit 9: busy sending
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localparam IO_PORT_IN_bit = 3; // R: GPIO port in
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localparam IO_PORT_OUT_bit = 4; // RW: GPIO port out
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localparam IO_PORT_DIR_bit = 5; // RW: GPIO port dir
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// localparam IO_CYCLES_bit = 6;
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assign io_rdata =
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(io_word_address[IO_UART_DAT_bit ] ? {22'd0, serial_busy, serial_valid, serial_data} : 32'd0) |
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(io_word_address[IO_UART_CNTL_bit] ? {22'd0, serial_busy, serial_valid, serial_data} : 32'd0) |
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(io_word_address[IO_PORT_IN_bit] ? port_in : 32'd0) |
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(io_word_address[IO_PORT_OUT_bit] ? port_out : 32'd0) |
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(io_word_address[IO_PORT_DIR_bit] ? port_dir : 32'd0) |
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// (io_word_address[IO_CYCLES_bit] ? cycles : 32'd0) |
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(io_word_address[IO_LEDS_bit] ? LEDs : 32'd0);
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always @(posedge clk)
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begin
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if (io_wstrb && io_word_address[IO_LEDS_bit]) LEDs <= io_wdata;
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if (io_wstrb && io_word_address[IO_PORT_OUT_bit]) port_out <= io_wdata;
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if (io_wstrb && io_word_address[IO_PORT_DIR_bit]) port_dir <= io_wdata;
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end
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// For now, we got no device that has blocking reads or writes
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assign io_rbusy = 0 ;
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assign io_wbusy = 0 ;
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/***************************************************************************************************
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/*
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* Memory and memory interface
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* memory map:
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* address[21:2] RAM word address (4 Mb max).
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* address[23:22] 00: RAM
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* 01: IO page (1-hot) (starts at 0x400000)
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* 10: SPI Flash page (starts at 0x800000)
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*/
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// The memory bus.
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wire [31:0] mem_address; // 24 bits are used internally. The two LSBs are ignored (using word addresses)
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wire [3:0] mem_wmask; // mem write mask and strobe /write Legal values are 000,0001,0010,0100,1000,0011,1100,1111
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wire [31:0] mem_rdata; // processor <- (mem and peripherals)
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wire [31:0] mem_wdata; // processor -> (mem and peripherals)
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wire mem_rstrb; // mem read strobe. Goes high to initiate memory read.
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wire mem_rbusy; // processor <- (mem and peripherals). Stays high until a read transfer is finished.
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wire mem_wbusy; // processor <- (mem and peripherals). Stays high until a write transfer is finished.
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wire mem_wstrb = |mem_wmask; // mem write strobe, goes high to initiate memory write (deduced from wmask)
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// IO bus.
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wire mem_address_is_ram = (mem_address[23:22] == 2'b00);
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wire mem_address_is_io = (mem_address[23:22] == 2'b01);
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wire mem_address_is_spi_flash = (mem_address[23:22] == 2'b10);
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wire mapped_spi_flash_rbusy;
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wire [31:0] mapped_spi_flash_rdata;
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MappedSPIFlash mapped_spi_flash(
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.clk(clk),
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.rstrb(mem_rstrb && mem_address_is_spi_flash),
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.word_address(mem_address[21:2]),
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.rdata(mapped_spi_flash_rdata),
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.rbusy(mapped_spi_flash_rbusy),
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.CLK(spi_clk),
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.CS_N(spi_cs_n),
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.IO({spi_miso,spi_mosi})
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);
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wire [31:0] io_rdata;
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wire [31:0] io_wdata = mem_wdata;
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wire io_rstrb = mem_rstrb && mem_address_is_io;
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wire io_wstrb = mem_wstrb && mem_address_is_io;
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wire [19:0] io_word_address = mem_address[21:2]; // word offset in io page
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wire io_rbusy;
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wire io_wbusy;
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assign mem_rbusy = io_rbusy | mapped_spi_flash_rbusy ;
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assign mem_wbusy = io_wbusy;
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wire [19:0] ram_word_address = mem_address[21:2];
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reg [31:0] RAM[(6144/4)-1:0];
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reg [31:0] ram_rdata;
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always @(posedge clk) begin
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if(mem_address_is_ram) begin
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if(mem_wmask[0]) RAM[ram_word_address][ 7:0 ] <= mem_wdata[ 7:0 ];
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if(mem_wmask[1]) RAM[ram_word_address][15:8 ] <= mem_wdata[15:8 ];
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if(mem_wmask[2]) RAM[ram_word_address][23:16] <= mem_wdata[23:16];
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if(mem_wmask[3]) RAM[ram_word_address][31:24] <= mem_wdata[31:24];
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end
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ram_rdata <= RAM[ram_word_address];
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end
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assign mem_rdata = mem_address_is_io ? io_rdata :
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mem_address_is_ram ? ram_rdata :
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mapped_spi_flash_rdata;
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/****************************************************************/
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/* And last but not least, the processor */
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FemtoRV32 #(
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.ADDR_WIDTH(24)
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) processor(
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.clk(clk),
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.mem_addr(mem_address),
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.mem_wdata(mem_wdata),
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.mem_wmask(mem_wmask),
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.mem_rdata(mem_rdata),
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.mem_rstrb(mem_rstrb),
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.mem_rbusy(mem_rbusy),
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.mem_wbusy(mem_wbusy),
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.reset(resetq)
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);
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endmodule
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