34 lines
808 B
Verilog
34 lines
808 B
Verilog
module femtoPLL #(
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parameter freq = 54 // Default to 54 MHz
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) (
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input wire pclk,
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output wire clk
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);
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// Tang Primer 20K (GW2A-18) PLL Configuration
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// Input: 27 MHz
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// Output: 54 MHz
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rPLL #(
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.FCLKIN("27"),
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.DEVICE("GW2A-18"),
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.IDIV_SEL(0), // Input Divider = 1
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.FBDIV_SEL(15), // Feedback Divider = 16 (VCO = 27*1*16 = 432 MHz)
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.ODIV_SEL(8) // Output Divider = 8 (Out = 432/8 = 54 MHz)
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) pll_i (
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.CLKOUTP(),
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.CLKOUTD(),
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.CLKOUTD3(),
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.RESET(1'b0),
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.RESET_P(1'b0),
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.CLKFB(1'b0),
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.FBDSEL(6'b0),
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.IDSEL(6'b0),
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.ODSEL(6'b0),
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.PSDA(4'b0),
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.DUTYDA(4'b0),
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.FDLY(4'b0),
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.CLKIN(pclk),
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.CLKOUT(clk)
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);
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endmodule
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