verilog

2024-04-13 05:48:55 +03:00
commit ed465dd690
61 changed files with 2719 additions and 0 deletions
--- a/lab2/impl/gwsynthesis/lab2.log
+++ b/lab2/impl/gwsynthesis/lab2.log
@ -0,0 +1,24 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v'
+Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1)
+NOTE  (EX0101) : Current top module is "BitM"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
+[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
+GowinSynthesis finish
--- a/lab2/impl/gwsynthesis/lab2.prj
+++ b/lab2/impl/gwsynthesis/lab2.prj
@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
+    <FileList>
+        <File path="C:\cygwin64\home\koray\verilog\lab2\src\BitM.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="0"/>
+        <Option type="global_freq" value="100.000"/>
+        <Option type="looplimit" value="2000"/>
+        <Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
+        <Option type="print_all_synthesis_warning" value="0"/>
+        <Option type="ram_rw_check" value="0"/>
+        <Option type="verilog_language" value="verilog-2001"/>
+        <Option type="vhdl_language" value="vhdl-1993"/>
+    </OptionList>
+</Project>
--- a/lab2/impl/gwsynthesis/lab2.vg
+++ b/lab2/impl/gwsynthesis/lab2.vg
@ -0,0 +1,76 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 11 07:46:56 2024
+
+//Source file index table:
+//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v"
+`timescale 100 ps/100 ps
+module BitM (
+  A,
+  B,
+  AlB,
+  AeB,
+  AgB
+)
+;
+input A;
+input B;
+output AlB;
+output AeB;
+output AgB;
+wire A_d;
+wire B_d;
+wire AlB_d;
+wire AgB_d;
+wire AeB_d;
+wire VCC;
+wire GND;
+  IBUF A_ibuf (
+    .O(A_d),
+    .I(A) 
+);
+  IBUF B_ibuf (
+    .O(B_d),
+    .I(B) 
+);
+  OBUF AlB_obuf (
+    .O(AlB),
+    .I(AlB_d) 
+);
+  OBUF AeB_obuf (
+    .O(AeB),
+    .I(AeB_d) 
+);
+  OBUF AgB_obuf (
+    .O(AgB),
+    .I(AgB_d) 
+);
+  LUT2 AlB_d_s (
+    .F(AlB_d),
+    .I0(A_d),
+    .I1(B_d) 
+);
+defparam AlB_d_s.INIT=4'h4;
+  LUT2 AgB_d_s (
+    .F(AgB_d),
+    .I0(B_d),
+    .I1(A_d) 
+);
+defparam AgB_d_s.INIT=4'h4;
+  LUT2 AeB_d_s (
+    .F(AeB_d),
+    .I0(A_d),
+    .I1(B_d) 
+);
+defparam AeB_d_s.INIT=4'h9;
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* BitM */
--- a/lab2/impl/gwsynthesis/lab2_syn.rpt.html
+++ b/lab2/impl/gwsynthesis/lab2_syn.rpt.html
@ -0,0 +1,167 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>synthesis Report</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
+div#main_wrapper{ width: 100%; }
+div#content { margin-left: 350px; margin-right: 30px; }
+div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
+div#catalog ul { list-style-type: none; }
+div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
+div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
+div#catalog a:visited { color: #0084ff; }
+div#catalog a:hover { color: #fff; background: #0084ff; }
+hr { margin-top: 30px; margin-bottom: 30px; }
+h1, h3 { text-align: center; }
+h1 {margin-top: 50px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { padding: 5px 5px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
+table.detail_table td.label { min-width: 100px; width: 8%;}
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="catalog_wrapper">
+<div id="catalog">
+<ul>
+<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
+<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
+<li><a href="#resource" style=" font-size: 16px;">Resource</a>
+<ul>
+<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
+<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
+</ul>
+</li>
+</ul>
+</div><!-- catalog -->
+</div><!-- catalog_wrapper -->
+<div id="content">
+<h1><a name="about">Synthesis Messages</a></h1>
+<table class="summary_table">
+<tr>
+<td class="label">Report Title</td>
+<td>GowinSynthesis Report</td>
+</tr>
+<tr>
+<td class="label">Design File</td>
+<td>C:\cygwin64\home\koray\verilog\lab2\src\BitM.v<br>
+</td>
+</tr>
+<tr>
+<td class="label">GowinSynthesis Constraints File</td>
+<td>---</td>
+</tr>
+<tr>
+<td class="label">Tool Version</td>
+<td>V1.9.9.02</td>
+</tr>
+<tr>
+<td class="label">Part Number</td>
+<td>GW2A-LV18PG256C8/I7</td>
+</tr>
+<tr>
+<td class="label">Device</td>
+<td>GW2A-18</td>
+</tr>
+<tr>
+<td class="label">Device Version</td>
+<td>C</td>
+</tr>
+<tr>
+<td class="label">Created Time</td>
+<td>Thu Apr 11 07:46:56 2024
+</td>
+</tr>
+<tr>
+<td class="label">Legal Announcement</td>
+<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
+</tr>
+</table>
+<h1><a name="summary">Synthesis Details</a></h1>
+<table class="summary_table">
+<tr>
+<td class="label">Top Level Module</td>
+<td>BitM</td>
+</tr>
+<tr>
+<td class="label">Synthesis Process</td>
+<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB<br/></td>
+</tr>
+<tr>
+<td class="label">Total Time and Memory Usage</td>
+<td>CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB</td>
+</tr>
+</table>
+<h1><a name="resource">Resource</a></h1>
+<h2><a name="usage">Resource Usage Summary</a></h2>
+<table class="summary_table">
+<tr>
+<td class="label"><b>Resource</b></td>
+<td><b>Usage</b></td>
+</tr>
+<tr>
+<td class="label"><b>I/O Port </b></td>
+<td>5</td>
+</tr>
+<tr>
+<td class="label"><b>I/O Buf </b></td>
+<td>5</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
+<td>2</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
+<td>3</td>
+</tr>
+<tr>
+<td class="label"><b>LUT </b></td>
+<td>3</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
+<td>3</td>
+</tr>
+</table>
+<h2><a name="utilization">Resource Utilization Summary</a></h2>
+<table class="summary_table">
+<tr>
+<td class="label"><b>Resource</b></td>
+<td><b>Usage</b></td>
+<td><b>Utilization</b></td>
+</tr>
+<tr>
+<td class="label">Logic</td>
+<td>3(3 LUT, 0 ALU) / 20736</td>
+<td><1%</td>
+</tr>
+<tr>
+<td class="label">Register</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp--Register as Latch</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp--Register as FF</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">BSRAM</td>
+<td>0 / 46</td>
+<td>0%</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>
--- a/lab2/impl/gwsynthesis/lab2_syn_resource.html
+++ b/lab2/impl/gwsynthesis/lab2_syn_resource.html
@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">3</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>
--- a/lab2/impl/gwsynthesis/lab2_syn_rsc.xml
+++ b/lab2/impl/gwsynthesis/lab2_syn_rsc.xml
@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="BitM" Lut="3" T_Lut="3(3)"/>
--- a/lab2/impl/lab2_process_config.json
+++ b/lab2/impl/lab2_process_config.json
@ -0,0 +1,88 @@
+{
+ "BACKGROUND_PROGRAMMING" : "off",
+ "COMPRESS" : false,
+ "CPU" : false,
+ "CRC_CHECK" : true,
+ "Clock_Route_Order" : 0,
+ "Correct_Hold_Violation" : true,
+ "DONE" : false,
+ "DOWNLOAD_SPEED" : "default",
+ "Disable_Insert_Pad" : false,
+ "ENABLE_CTP" : false,
+ "ENABLE_MERGE_MODE" : false,
+ "ENCRYPTION_KEY" : false,
+ "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
+ "ERROR_DECTION_AND_CORRECTION" : false,
+ "ERROR_DECTION_ONLY" : false,
+ "ERROR_INJECTION" : false,
+ "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
+ "Enable_DSRM" : false,
+ "FORMAT" : "binary",
+ "FREQUENCY_DIVIDER" : "",
+ "Generate_Constraint_File_of_Ports" : false,
+ "Generate_IBIS_File" : false,
+ "Generate_Plain_Text_Timing_Report" : false,
+ "Generate_Post_PNR_Simulation_Model_File" : false,
+ "Generate_Post_Place_File" : false,
+ "Generate_SDF_File" : false,
+ "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
+ "Global_Freq" : "default",
+ "GwSyn_Loop_Limit" : 2000,
+ "HOTBOOT" : false,
+ "I2C" : false,
+ "I2C_SLAVE_ADDR" : "00",
+ "IncludePath" : [
+
+ ],
+ "Incremental_Compile" : "",
+ "Initialize_Primitives" : false,
+ "JTAG" : false,
+ "MODE_IO" : false,
+ "MSPI" : false,
+ "MSPI_JUMP" : false,
+ "MULTIBOOT_ADDRESS_WIDTH" : "24",
+ "MULTIBOOT_MODE" : "Normal",
+ "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
+ "MULTIJUMP_ADDRESS_WIDTH" : "24",
+ "MULTIJUMP_MODE" : "Normal",
+ "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
+ "Multi_Boot" : true,
+ "OUTPUT_BASE_NAME" : "lab2",
+ "POWER_ON_RESET_MONITOR" : true,
+ "PRINT_BSRAM_VALUE" : true,
+ "PROGRAM_DONE_BYPASS" : false,
+ "PlaceInRegToIob" : true,
+ "PlaceIoRegToIob" : true,
+ "PlaceOutRegToIob" : true,
+ "Place_Option" : "0",
+ "Process_Configuration_Verion" : "1.0",
+ "Promote_Physical_Constraint_Warning_to_Error" : true,
+ "READY" : false,
+ "RECONFIG_N" : false,
+ "Ram_RW_Check" : false,
+ "Replicate_Resources" : false,
+ "Report_Auto-Placed_Io_Information" : false,
+ "Route_Maxfan" : 23,
+ "Route_Option" : "0",
+ "Run_Timing_Driven" : true,
+ "SECURE_MODE" : false,
+ "SECURITY_BIT" : true,
+ "SEU_HANDLER" : false,
+ "SEU_HANDLER_CHECKSUM" : false,
+ "SEU_HANDLER_MODE" : "auto",
+ "SSPI" : false,
+ "STOP_SEU_HANDLER" : false,
+ "Show_All_Warnings" : false,
+ "Synthesize_tool" : "GowinSyn",
+ "TclPre" : "",
+ "TopModule" : "",
+ "USERCODE" : "default",
+ "Unused_Pin" : "As_input_tri_stated_with_pull_up",
+ "VCCAUX" : 3.3,
+ "VCCX" : "3.3",
+ "VHDL_Standard" : "VHDL_Std_1993",
+ "Verilog_Standard" : "Vlg_Std_2001",
+ "WAKE_UP" : "0",
+ "show_all_warnings" : false,
+ "turn_off_bg" : false
+}
--- a/lab2/impl/temp/rtl_parser.result
+++ b/lab2/impl/temp/rtl_parser.result
@ -0,0 +1,36 @@
+[
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
+  "InstLine" : 1,
+  "InstName" : "BitM",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "BitM"
+ },
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
+  "InstLine" : 1,
+  "InstName" : "fullAdder",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "fullAdder"
+ },
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+  "InstLine" : 1,
+  "InstName" : "tb",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "tb",
+  "SubInsts" : [
+   {
+    "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+    "InstLine" : 6,
+    "InstName" : "uut",
+    "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "halfAdder"
+   }
+  ]
+ }
+]
--- a/lab2/impl/temp/rtl_parser_arg.json
+++ b/lab2/impl/temp/rtl_parser_arg.json
@ -0,0 +1,29 @@
+{
+ "Device" : "GW2A-18C",
+ "Files" : [
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+   "Type" : "verilog"
+  }
+ ],
+ "IncludePath" : [
+
+ ],
+ "LoopLimit" : 2000,
+ "ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
+ "Top" : "",
+ "VerilogStd" : "verilog_2001",
+ "VhdlStd" : "vhdl_93"
+}
--- a/lab2/lab2.gprj
+++ b/lab2/lab2.gprj
@ -0,0 +1,13 @@
+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE gowin-fpga-project>
+<Project>
+    <Template>FPGA</Template>
+    <Version>5</Version>
+    <Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
+    <FileList>
+        <File path="src/BitM.v" type="file.verilog" enable="1"/>
+        <File path="src/fullAdder.v" type="file.verilog" enable="1"/>
+        <File path="src/halfAdder.v" type="file.verilog" enable="1"/>
+        <File path="src/tb.v" type="file.verilog" enable="1"/>
+    </FileList>
+</Project>
--- a/lab2/lab2.gprj.user
+++ b/lab2/lab2.gprj.user
@ -0,0 +1,17 @@
+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE ProjectUserData>
+<UserConfig>
+    <Version>1.0</Version>
+    <FlowState>
+        <Process ID="Synthesis" State="4"/>
+        <Process ID="Pnr" State="0"/>
+        <Process ID="Gao" State="0"/>
+        <Process ID="Rtl_Gao" State="2"/>
+    </FlowState>
+    <ResultFileList>
+        <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
+        <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
+        <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
+    </ResultFileList>
+    <Ui>000000ff00000001fd00000002000000000000010000000130fc0200000001fc00000063000001300000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000121fc0100000001fc00000000000005000000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000003f80000013000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
+</UserConfig>
--- a/lab2/src/BitM.v
+++ b/lab2/src/BitM.v
@ -0,0 +1,19 @@
+module BitM(
+  input A,
+  input B,
+  output AlB,
+  output AeB,
+  output AgB  
+);
+
+    wire An, Bn;
+
+    not n1 (An, A);
+    not n2 (Bn, B);
+
+    and a1 (AlB, An, B);
+    and a2 (AgB, Bn, A);
+
+    nor nor1 (AeB, AlB, AgB);
+
+endmodule
--- a/lab2/src/BitM_tb.v
+++ b/lab2/src/BitM_tb.v
@ -0,0 +1,26 @@
+module BitM_tb();
+
+reg r1, r2;
+wire w1, w2, w3;
+
+BitM uut(
+    .A(r1),
+    .B(r2),
+    .AlB(w1),
+    .AeB(w2),
+    .AgB(w3)
+);
+
+initial begin
+    $dumpfile("bdmp.vcd");
+    $dumpvars;
+    r1 = 0; r2 = 0; #10
+    r1 = 0; r2 = 1; #10
+    r1 = 1; r2 = 0; #10
+    r1 = 1; r2 = 1; #10
+    $display(w1);
+    $display(w2);
+    $display(w3);
+end
+
+endmodule
--- a/lab2/src/bdmp.vcd
+++ b/lab2/src/bdmp.vcd
@ -0,0 +1,58 @@
+$date
+	Thu Apr 11 07:50:26 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module BitM_tb $end
+$var wire 1 ! w3 $end
+$var wire 1 " w2 $end
+$var wire 1 # w1 $end
+$var reg 1 $ r1 $end
+$var reg 1 % r2 $end
+$scope module uut $end
+$var wire 1 $ A $end
+$var wire 1 " AeB $end
+$var wire 1 ! AgB $end
+$var wire 1 # AlB $end
+$var wire 1 & An $end
+$var wire 1 % B $end
+$var wire 1 ' Bn $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+1'
+1&
+0%
+0$
+0#
+1"
+0!
+$end
+#10
+0"
+0'
+1#
+1%
+#20
+1!
+0"
+1'
+0#
+0&
+0%
+1$
+#30
+1"
+0!
+0'
+1%
+#40
--- a/lab2/src/blab2
+++ b/lab2/src/blab2
@ -0,0 +1,70 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000002114102cad0 .scope module, "BitM_tb" "BitM_tb" 2 1;
+ .timescale 0 0;
+v0000021140f146e0_0 .var "r1", 0 0;
+v0000021140f14780_0 .var "r2", 0 0;
+v0000021140f14820_0 .net "w1", 0 0, L_0000021140ee32f0;  1 drivers
+v0000021140f148c0_0 .net "w2", 0 0, L_0000021140f14f60;  1 drivers
+v0000021140f14960_0 .net "w3", 0 0, L_0000021140f14de0;  1 drivers
+S_000002114102cc60 .scope module, "uut" "BitM" 2 6, 3 1 0, S_000002114102cad0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "AlB";
+    .port_info 3 /OUTPUT 1 "AeB";
+    .port_info 4 /OUTPUT 1 "AgB";
+L_000002114102af60 .functor NOT 1, v0000021140f146e0_0, C4<0>, C4<0>, C4<0>;
+L_0000021140ee3190 .functor NOT 1, v0000021140f14780_0, C4<0>, C4<0>, C4<0>;
+L_0000021140ee32f0 .functor AND 1, L_000002114102af60, v0000021140f14780_0, C4<1>, C4<1>;
+L_0000021140f14de0 .functor AND 1, L_0000021140ee3190, v0000021140f146e0_0, C4<1>, C4<1>;
+L_0000021140f14f60 .functor NOR 1, L_0000021140ee32f0, L_0000021140f14de0, C4<0>, C4<0>;
+v0000021141028fc0_0 .net "A", 0 0, v0000021140f146e0_0;  1 drivers
+v0000021140ee2ee0_0 .net "AeB", 0 0, L_0000021140f14f60;  alias, 1 drivers
+v000002114102aec0_0 .net "AgB", 0 0, L_0000021140f14de0;  alias, 1 drivers
+v000002114102cdf0_0 .net "AlB", 0 0, L_0000021140ee32f0;  alias, 1 drivers
+v000002114102ce90_0 .net "An", 0 0, L_000002114102af60;  1 drivers
+v0000021140f145a0_0 .net "B", 0 0, v0000021140f14780_0;  1 drivers
+v0000021140f14640_0 .net "Bn", 0 0, L_0000021140ee3190;  1 drivers
+    .scope S_000002114102cad0;
+T_0 ;
+    %vpi_call 2 15 "$dumpfile", "bdmp.vcd" {0 0 0};
+    %vpi_call 2 16 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000021140f146e0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000021140f14780_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000021140f146e0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000021140f14780_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000021140f146e0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000021140f14780_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000021140f146e0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000021140f14780_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 21 "$display", v0000021140f14820_0 {0 0 0};
+    %vpi_call 2 22 "$display", v0000021140f148c0_0 {0 0 0};
+    %vpi_call 2 23 "$display", v0000021140f14960_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "BitM_tb.v";
+    "BitM.v";
--- a/lab2/src/dmp.vcd
+++ b/lab2/src/dmp.vcd
@ -0,0 +1,43 @@
+$date
+	Thu Apr 11 06:36:34 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module tb $end
+$var wire 1 ! w2 $end
+$var wire 1 " w1 $end
+$var reg 1 # r1 $end
+$var reg 1 $ r2 $end
+$scope module uut $end
+$var wire 1 # A $end
+$var wire 1 $ B $end
+$var wire 1 ! C $end
+$var wire 1 " S $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+0$
+0#
+0"
+0!
+$end
+#20
+1"
+1#
+#40
+1$
+0#
+#60
+0"
+1!
+1#
+#80
--- a/lab2/src/fdmp.vcd
+++ b/lab2/src/fdmp.vcd
@ -0,0 +1,75 @@
+$date
+	Thu Apr 11 07:39:27 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ftb $end
+$var wire 1 ! w2 $end
+$var wire 1 " w1 $end
+$var reg 1 # r1 $end
+$var reg 1 $ r2 $end
+$var reg 1 % r3 $end
+$scope module uut $end
+$var wire 1 # A $end
+$var wire 1 & AB $end
+$var wire 1 ' ABCin $end
+$var wire 1 ( AaB $end
+$var wire 1 $ B $end
+$var wire 1 % Cin $end
+$var wire 1 ! Cout $end
+$var wire 1 " S $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+0(
+0'
+0&
+0%
+0$
+0#
+0"
+0!
+$end
+#10
+1"
+1%
+#20
+1&
+0%
+1$
+#30
+1!
+0"
+1'
+1%
+#40
+0!
+1"
+0'
+0%
+0$
+1#
+#50
+1!
+0"
+1'
+1%
+#60
+0'
+0&
+1(
+0%
+1$
+#70
+1"
+1%
+#80
--- a/lab2/src/flab2
+++ b/lab2/src/flab2
@ -0,0 +1,106 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000001da0354ad70 .scope module, "ftb" "ftb" 2 1;
+ .timescale 0 0;
+v000001da035dc840_0 .var "r1", 0 0;
+v000001da035dc8e0_0 .var "r2", 0 0;
+v000001da035dc980_0 .var "r3", 0 0;
+v000001da035dca20_0 .net "w1", 0 0, L_000001da03594080;  1 drivers
+v000001da035935f0_0 .net "w2", 0 0, L_000001da03594470;  1 drivers
+S_000001da0354e9e0 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_000001da0354ad70;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /INPUT 1 "Cin";
+    .port_info 3 /OUTPUT 1 "S";
+    .port_info 4 /OUTPUT 1 "Cout";
+L_000001da03594010 .functor XOR 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<0>, C4<0>;
+L_000001da03594080 .functor XOR 1, L_000001da03594010, v000001da035dc980_0, C4<0>, C4<0>;
+L_000001da03593e50 .functor AND 1, L_000001da03594010, v000001da035dc980_0, C4<1>, C4<1>;
+L_000001da035940f0 .functor AND 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<1>, C4<1>;
+L_000001da03594470 .functor OR 1, L_000001da03593e50, L_000001da035940f0, C4<0>, C4<0>;
+v000001da03563310_0 .net "A", 0 0, v000001da035dc840_0;  1 drivers
+v000001da03562ee0_0 .net "AB", 0 0, L_000001da03594010;  1 drivers
+v000001da0354af00_0 .net "ABCin", 0 0, L_000001da03593e50;  1 drivers
+v000001da03549850_0 .net "AaB", 0 0, L_000001da035940f0;  1 drivers
+v000001da0354eb70_0 .net "B", 0 0, v000001da035dc8e0_0;  1 drivers
+v000001da0354ec10_0 .net "Cin", 0 0, v000001da035dc980_0;  1 drivers
+v000001da0354ecb0_0 .net "Cout", 0 0, L_000001da03594470;  alias, 1 drivers
+v000001da0354ed50_0 .net "S", 0 0, L_000001da03594080;  alias, 1 drivers
+    .scope S_000001da0354ad70;
+T_0 ;
+    %vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
+    %vpi_call 2 16 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc840_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc8e0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001da035dc980_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 25 "$display", v000001da035dca20_0 {0 0 0};
+    %vpi_call 2 26 "$display", v000001da035935f0_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "ftb.v";
+    "fullAdder.v";
--- a/lab2/src/ftb.v
+++ b/lab2/src/ftb.v
@ -0,0 +1,29 @@
+module ftb ();
+
+reg r1, r2, r3;
+wire w1, w2;
+
+fullAdder uut(
+    .A(r1),
+    .B(r2),
+    .Cin(r3),
+    .S(w1),
+    .Cout(w2)
+);
+
+initial begin
+    $dumpfile("fdmp.vcd");
+    $dumpvars;
+    r1 = 0; r2 = 0; r3 = 0; #10
+    r1 = 0; r2 = 0; r3 = 1; #10
+    r1 = 0; r2 = 1; r3 = 0; #10
+    r1 = 0; r2 = 1; r3 = 1; #10
+    r1 = 1; r2 = 0; r3 = 0; #10
+    r1 = 1; r2 = 0; r3 = 1; #10
+    r1 = 1; r2 = 1; r3 = 0; #10
+    r1 = 1; r2 = 1; r3 = 1; #10
+    $display(w1);
+    $display(w2);
+end
+
+endmodule
--- a/lab2/src/fullAdder.v
+++ b/lab2/src/fullAdder.v
@ -0,0 +1,20 @@
+module fullAdder(
+  input A,
+  input B,
+  input Cin,
+  output S,
+  output Cout  
+);
+
+    wire AB;
+    wire ABCin, AaB;
+
+    xor (AB, A, B);
+    xor (S, AB, Cin);
+
+    and (ABCin, AB, Cin);
+    and (AaB, A, B);
+
+    or (Cout, ABCin, AaB);
+
+endmodule
--- a/lab2/src/halfAdder.v
+++ b/lab2/src/halfAdder.v
@ -0,0 +1,11 @@
+module halfAdder(
+  input A,
+  input B,
+  output S,
+  output C  
+);
+
+    xor (S, A, B);
+    and (C, A, B);
+
+endmodule
--- a/lab2/src/lab2
+++ b/lab2/src/lab2
@ -0,0 +1,61 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000001b4458eec80 .scope module, "tb" "tb" 2 1;
+ .timescale 0 0;
+v000001b4458ec1d0_0 .var "r1", 0 0;
+v000001b4458ec270_0 .var "r2", 0 0;
+v000001b4458ec310_0 .net "w1", 0 0, L_000001b445783190;  1 drivers
+v000001b4458ec3b0_0 .net "w2", 0 0, L_000001b4457832f0;  1 drivers
+S_000001b4458eee10 .scope module, "uut" "halfAdder" 2 6, 3 1 0, S_000001b4458eec80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "S";
+    .port_info 3 /OUTPUT 1 "C";
+L_000001b445783190 .functor XOR 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<0>, C4<0>;
+L_000001b4457832f0 .functor AND 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<1>, C4<1>;
+v000001b4458ebff0_0 .net "A", 0 0, v000001b4458ec1d0_0;  1 drivers
+v000001b445782ee0_0 .net "B", 0 0, v000001b4458ec270_0;  1 drivers
+v000001b4458ec090_0 .net "C", 0 0, L_000001b4457832f0;  alias, 1 drivers
+v000001b4458ec130_0 .net "S", 0 0, L_000001b445783190;  alias, 1 drivers
+    .scope S_000001b4458eec80;
+T_0 ;
+    %vpi_call 2 14 "$dumpfile", "dmp.vcd" {0 0 0};
+    %vpi_call 2 15 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001b4458ec1d0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001b4458ec270_0, 0, 1;
+    %delay 20, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001b4458ec1d0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001b4458ec270_0, 0, 1;
+    %delay 20, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001b4458ec1d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001b4458ec270_0, 0, 1;
+    %delay 20, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001b4458ec1d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001b4458ec270_0, 0, 1;
+    %delay 20, 0;
+    %vpi_call 2 20 "$display", v000001b4458ec310_0 {0 0 0};
+    %vpi_call 2 21 "$display", v000001b4458ec3b0_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "tb.v";
+    "halfAdder.v";
--- a/lab2/src/tb.v
+++ b/lab2/src/tb.v
@ -0,0 +1,24 @@
+module tb();
+
+reg r1, r2;
+wire w1, w2;
+
+halfAdder uut(
+    .A(r1),
+    .B(r2),
+    .S(w1),
+    .C(w2)
+);
+
+initial begin
+    $dumpfile("dmp.vcd");
+    $dumpvars;
+    r1 = 0; r2 = 0; #20
+    r1 = 1; r2 = 0; #20
+    r1 = 0; r2 = 1; #20
+    r1 = 1; r2 = 1; #20
+    $display(w1);
+    $display(w2);
+end
+
+endmodule