kaltinsoy/verilog
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k0rrluna ed465dd690 verilog
2024-04-13 05:48:55 +03:00
lab2
verilog
2024-04-13 05:48:55 +03:00
lab2_prep
verilog
2024-04-13 05:48:55 +03:00
lab3
verilog
2024-04-13 05:48:55 +03:00
test
verilog
2024-04-13 05:48:55 +03:00
a.out
verilog
2024-04-13 05:48:55 +03:00
dmp.vcd
verilog
2024-04-13 05:48:55 +03:00
hello_tb.v
verilog
2024-04-13 05:48:55 +03:00
hello.v
verilog
2024-04-13 05:48:55 +03:00
Description
No description provided
2 MiB
Languages
Verilog 99.2%
Shell 0.5%
Coq 0.3%