kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

verilog

Browse Source
This commit is contained in:
k0rrluna
2024-04-13 05:48:55 +03:00
commit ed465dd690
61 changed files with 2719 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
lab3/impl/gwsynthesis/lab3.log Normal file
View File

@@ -0,0 +1,23 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v'
ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
Sorry, too many errors..
GowinSynthesis finish