verilog

test/a.out

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+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+S_000001c04a3a6760 .scope module, "tb" "tb" 2 1;
+ .timescale 0 0;
+v000001c04a3a6b20_0 .var "r1", 0 0;
+v000001c04a51ba60_0 .var "r2", 0 0;
+v000001c04a51bb00_0 .net "w1", 0 0, L_000001c04a518b00;  1 drivers
+v000001c04a51bba0_0 .net "w2", 0 0, L_000001c04a518d50;  1 drivers
+v000001c04a51bc40_0 .net "w3", 0 0, L_000001c04a517170;  1 drivers
+S_000001c04a3a68f0 .scope module, "uut" "test" 2 6, 3 1 0, S_000001c04a3a6760;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A";
+    .port_info 1 /INPUT 1 "B";
+    .port_info 2 /OUTPUT 1 "LED1";
+    .port_info 3 /OUTPUT 1 "LED2";
+    .port_info 4 /OUTPUT 1 "LED3";
+L_000001c04a518b00 .functor BUFZ 1, v000001c04a3a6b20_0, C4<0>, C4<0>, C4<0>;
+L_000001c04a518d50 .functor BUFZ 1, v000001c04a51ba60_0, C4<0>, C4<0>, C4<0>;
+L_000001c04a517170 .functor OR 1, v000001c04a3a6b20_0, v000001c04a51ba60_0, C4<0>, C4<0>;
+v000001c04a519860_0 .net "A", 0 0, v000001c04a3a6b20_0;  1 drivers
+v000001c04a516ec0_0 .net "B", 0 0, v000001c04a51ba60_0;  1 drivers
+v000001c04a518cb0_0 .net "LED1", 0 0, L_000001c04a518b00;  alias, 1 drivers
+v000001c04a518a60_0 .net "LED2", 0 0, L_000001c04a518d50;  alias, 1 drivers
+v000001c04a3a6a80_0 .net "LED3", 0 0, L_000001c04a517170;  alias, 1 drivers
+    .scope S_000001c04a3a6760;
+T_0 ;
+    %vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
+    %vpi_call 2 18 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001c04a3a6b20_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001c04a51ba60_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001c04a3a6b20_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001c04a51ba60_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001c04a3a6b20_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001c04a51ba60_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 22 "$display", v000001c04a51bc40_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001c04a3a6b20_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001c04a51ba60_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 24 "$display", v000001c04a51bc40_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "tb.v";
+    "test.v";

test/dmp.vcd

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+$date
+	Sat Apr 06 17:45:47 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module tb $end
+$var wire 1 ! w3 $end
+$var wire 1 " w2 $end
+$var wire 1 # w1 $end
+$var reg 1 $ r1 $end
+$var reg 1 % r2 $end
+$scope module uut $end
+$var wire 1 $ A $end
+$var wire 1 % B $end
+$var wire 1 # LED1 $end
+$var wire 1 " LED2 $end
+$var wire 1 ! LED3 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+0%
+0$
+0#
+0"
+0!
+$end
+#10
+1!
+1"
+1%
+#20
+0"
+0%
+1#
+1$
+#30
+1"
+1%
+#40

test/tb.v

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+module tb();
+
+reg r1, r2;
+wire w1, w2, w3;
+
+test uut(
+    .A(r1),
+    .B(r2),
+    .LED1(w1),
+    .LED2(w2),
+    .LED3(w3)
+);
+
+// test uut(r1, r2, w1, w2, w3);
+
+initial begin
+    $dumpfile("dmp.vcd");
+    $dumpvars;
+    r1 = 0; r2 = 0; #10;
+    r1 = 0; r2 = 1; #10;
+    r1 = 1; r2 = 0; #10;
+    $display(w3);
+    r1 = 1; r2 = 1; #10;
+    $display(w3);
+end
+
+
+
+endmodule

test/test.v

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+module test(
+    input A,
+    input B,
+    output LED1,
+    output LED2,
+    output LED3
+);
+
+
+assign LED1 = A;
+assign LED2 = B;
+assign LED3 = A | B;
+
+/*
+buf(LED1, A);
+buf(LED2, B);
+and(LED3, A, B);
+*/
+
+endmodule