60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
// femtorv32, a minimalistic RISC-V RV32I core
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// Bruno Levy, 2020-2021
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//
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// This file: memory-mapped constants to query
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// hardware config.
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module HardwareConfig(
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input wire clk,
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input wire sel_memory, // available RAM
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input wire sel_devices, // configured devices
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input wire sel_cpuinfo, // CPU information
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output wire [31:0] rdata // read data
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);
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`include "HardwareConfig_bits.v"
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`ifdef NRV_COUNTER_WIDTH
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localparam counter_width = `NRV_COUNTER_WIDTH;
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`else
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localparam counter_width = 32;
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`endif
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// configured devices
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localparam NRV_DEVICES = 0
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`ifdef NRV_IO_LEDS
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| (1 << IO_LEDS_bit)
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`endif
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`ifdef NRV_IO_UART
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| (1 << IO_UART_DAT_bit) | (1 << IO_UART_CNTL_bit)
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`endif
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`ifdef NRV_IO_SSD1351_1331
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| (1 << IO_SSD1351_CNTL_bit) | (1 << IO_SSD1351_CMD_bit) | (1 << IO_SSD1351_DAT_bit)
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`endif
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`ifdef NRV_IO_MAX7219
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| (1 << IO_MAX7219_DAT_bit)
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`endif
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`ifdef NRV_IO_SPI_FLASH
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| (1 << IO_SPI_FLASH_bit)
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`endif
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`ifdef NRV_MAPPED_SPI_FLASH
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| (1 << IO_MAPPED_SPI_FLASH_bit)
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`endif
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`ifdef NRV_IO_SDCARD
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| (1 << IO_SDCARD_bit)
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`endif
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`ifdef NRV_IO_BUTTONS
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| (1 << IO_BUTTONS_bit)
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`endif
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`ifdef NRV_IO_FGA
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| (1 << IO_FGA_CNTL_bit) | (1 << IO_FGA_DAT_bit)
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`endif
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;
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assign rdata = sel_memory ? `NRV_RAM :
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sel_devices ? NRV_DEVICES :
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sel_cpuinfo ? (`NRV_FREQ << 16) | counter_width : 32'b0;
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endmodule
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