52 lines
1.3 KiB
Verilog
52 lines
1.3 KiB
Verilog
// femtorv32, a minimalistic RISC-V RV32I core
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// Bruno Levy, 2020-2021
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//
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// This file: driver for MAX7219 led matrix display
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module MAX7219(
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input wire clk, // system clock
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input wire wstrb, // write strobe
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input wire sel, // write ignored if low
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input wire [31:0] wdata, // data to be written
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output wire wbusy, // asserted if the driver is busy sending data
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// MAX7219 pins
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output wire DIN, // data in
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output wire CLK, // clock
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output wire CS // chip select
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);
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reg [2:0] divider;
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always @(posedge clk) begin
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divider <= divider + 1;
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end
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// clk=60MHz, slow_clk=60/8 MHz (max = 10 MHz)
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wire slow_clk = (divider == 3'b000);
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reg[4:0] bitcount; // 0 means idle
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initial bitcount = 0;
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reg[15:0] shifter;
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assign DIN = shifter[15];
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wire sending = |bitcount;
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assign wbusy = sending;
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assign CS = !sending;
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assign CLK = sending && slow_clk;
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always @(posedge clk) begin
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if(wstrb) begin
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if(sel) begin
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shifter <= wdata[15:0];
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bitcount <= 16;
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end
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end else begin
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if(sending && slow_clk) begin
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bitcount <= bitcount - 5'd1;
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shifter <= {shifter[14:0], 1'b0};
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end
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end
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end
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endmodule
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