40 lines
1.0 KiB
Verilog
40 lines
1.0 KiB
Verilog
module femtoPLL #(
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parameter freq = 50
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) (
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input wire pclk,
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output wire clk
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);
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wire clk_feedback;
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wire clk_internal;
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// .CLKFBOUT_MULT(8)
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// .CLKOUT0_DIVIDE(8*100/freq)
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PLLE2_ADV #(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_MULT(freq/5), // Multiply value for all CLKOUT (2-64)
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.CLKFBOUT_PHASE("0.0"), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKIN1_PERIOD("10.0"), // Input clock period in ns to ps resolution
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.CLKOUT0_DIVIDE(20),
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.CLKOUT0_DUTY_CYCLE("0.5"),
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.CLKOUT0_PHASE("0.0"),
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.REF_JITTER1("0.0"), // Reference input jitter in UI (0.000-0.999)
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.STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
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) genclock(
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.CLKOUT0(clk_internal),
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.CLKIN1(pclk),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.CLKFBIN(clk_feedback) // 1-bit input, feedback clock
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);
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BUFG bufg(
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.I(clk_internal),
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.O(clk)
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);
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endmodule
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