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learnFPGAProject/SOC_pnr.json
kaltinsoy 6e38a6c1af newStep.v
2025-11-27 04:28:54 +03:00

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"bits": [ 9285 ] ,
"attributes": {
"ROUTING": "X49Y1/CLK0;X49Y1/CLK0/GB00;5;X49Y1/CLK1;X49Y1/CLK1/GB00;5;X49Y1/CLK2;X49Y1/CLK2/GB00;5;X46Y1/CLK0;X46Y1/CLK0/GB00;5;X50Y1/CLK0;X50Y1/CLK0/GB00;5;X47Y1/CLK1;X47Y1/CLK1/GB00;5;X47Y1/CLK2;X47Y1/CLK2/GB00;5;X48Y1/CLK0;X48Y1/CLK0/GB00;5;X48Y1/CLK1;X48Y1/CLK1/GB00;5;X47Y3/GT00;X47Y10/GT00/SPINE0;5;X46Y1/GB00;X47Y1/GBO0/GT00;5;X48Y1/CLK2;X48Y1/CLK2/GB00;5;X50Y1/CLK1;X50Y1/CLK1/GB00;5;X29Y27/SPINE0;X29Y27/SPINE0/PCLKT0;5;X51Y13/GT00;X51Y10/GT00/SPINE0;5;X51Y1/GB00;X51Y1/GBO0/GT00;5;X50Y1/CLK2;X50Y1/CLK2/GB00;5;X26Y0/F6;;5",
"src": "clockworks.v:44.11-44.14",
"hdlname": "CW CLK"
}
},
"clk": {
"hide_name": 0,
"bits": [ 9279 ] ,
"attributes": {
"ROUTING": " ",
"src": "step5.v:6.9-6.12"
}
}
}
}
}
}
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