56 lines
1.1 KiB
Verilog
56 lines
1.1 KiB
Verilog
/*
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* The PLL, that generates the internal clock (high freq) from the
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* external one (lower freq).
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* Trying to make something that is portable between different boards
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* For now, ICEStick, ULX3S, ECP5 evaluation boards, FOMU supported.
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* WIP: IceFeather
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*/
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`ifdef BENCH_OR_LINT
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`define PASSTHROUGH_PLL
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`endif
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/*
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`ifdef TANGNANO9K
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`define PASSTHROUGH_PLL
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`endif
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*/
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/**********************************************************************/
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`ifdef PASSTHROUGH_PLL
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module femtoPLL #(
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parameter freq = 60
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) (
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input pclk,
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output clk
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);
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assign clk = pclk;
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endmodule
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`else
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`ifdef ICE_STICK
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`include "pll_icestick.v"
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`elsif ICE_BREAKER
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`include "pll_icebreaker.v"
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`elsif ICE_FEATHER
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`include "pll_icefeather.v"
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`elsif ICE_SUGAR
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`include "pll_icesugar.v"
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`elsif ULX3S
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`include "pll_ulx3s.v"
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`elsif ECP5_EVN
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`include "pll_ecp5_evn.v"
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`elsif FOMU
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`include "pll_fomu.v"
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`elsif ARTY
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`include "pll_arty.v"
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`elsif CMODA7
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`include "pll_cmod_a7.v"
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`elsif TANGNANO9K
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`include "pll_tangnano9k.v"
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`elsif PRIMER20K
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`include "pll_tangprimer20k.v"
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`endif
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`endif
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