150 lines
3.1 KiB
Verilog
150 lines
3.1 KiB
Verilog
// Configuration file for femtosoc/femtorv32
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`ifdef BENCH_VERILATOR
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`define BENCH
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`endif
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`ifdef ULX3S
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`include "CONFIGS/ulx3s_config.v"
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`endif
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`ifdef ICE_STICK
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`include "CONFIGS/icestick_config.v"
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`endif
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`ifdef ICE_BREAKER
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`include "CONFIGS/icebreaker_config.v"
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`endif
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`ifdef ECP5_EVN
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`include "CONFIGS/ecp5evn_config.v"
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`endif
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`ifdef ARTY
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`include "CONFIGS/arty_config.v"
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`endif
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`ifdef ICE_SUGAR_NANO
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`include "CONFIGS/icesugarnano_config.v"
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`endif
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`ifdef CMODA7
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`include "CONFIGS/cmod_a7_config.v"
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`endif
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`ifdef BENCH_VERILATOR
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`include "CONFIGS/bench_config.v"
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`endif
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`ifndef NRV_CONFIGURED
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`include "CONFIGS/generic_config.v"
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`endif
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/******************************************************************************/
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/*
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* Uncomment if the RESET button is wired and active low:
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* (wire a push button and a pullup resistor to
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* pin 47 or change in nanorv.pcf).
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*/
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`ifdef ICE_STICK
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//`define NRV_NEGATIVE_RESET
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`endif
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`ifdef FOMU
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`define NRV_NEGATIVE_RESET
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`endif
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`ifdef NRV_IO_SPI_FLASH
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`define NRV_SPI_FLASH
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`endif
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`ifdef NRV_MAPPED_SPI_FLASH
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`define NRV_SPI_FLASH
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`endif
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/*
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* On the ECP5 evaluation board, there is already a wired button, active low,
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* wired to the "P4" ball of the ECP5 (see ecp5_evn.lpf)
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*/
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`ifdef ECP5_EVN
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`define NRV_NEGATIVE_RESET
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`endif
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// Toggle FPGA defines (ICE40, ECP5) in function of board defines (ICE_STICK, ECP5_EVN)
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// Board defines are set in Makefile.
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`ifdef ICE_STICK
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`define ICE40
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`endif
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`ifdef ICE_BREAKER
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`define ICE40
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`endif
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`ifdef ICE_FEATHER
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`define ICE40
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`endif
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`ifdef ICE_SUGAR
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`define ICE40
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`endif
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`ifdef ICE_SUGAR_NANO
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`define ICE40
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`define PASSTHROUGH_PLL
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`endif
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`ifdef FOMU
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`define ICE40
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`endif
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`ifdef ECP5_EVN
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`define ECP5
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`endif
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`ifdef ULX3S
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`define ECP5
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`endif
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/******************************************************************************************************************/
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/* Processor */
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`define NRV_IS_IO_ADDR(addr) |addr[23:22] // Asserted if address is in IO space (then it needs additional wait states)
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`include "PROCESSOR/utils.v"
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`ifdef NRV_FEMTORV32_QUARK
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`include "PROCESSOR/femtorv32_quark.v" // Minimalistic version of the processor for IceStick (RV32I)
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`endif
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`ifdef NRV_FEMTORV32_QUARK_BICYCLE
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`include "PROCESSOR/femtorv32_quark_bicycle.v" // Quark with Matthias's 2 CPI mode and barrel shifter (RV32I)
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`endif
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`ifdef NRV_FEMTORV32_TACHYON
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`include "PROCESSOR/femtorv32_tachyon.v" // Version for the IceStick with higher maxfreq (RV32I)
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`endif
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`ifdef NRV_FEMTORV32_ELECTRON
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`include "PROCESSOR/femtorv32_electron.v" // RV32IM with barrel shifter
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`endif
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`ifdef NRV_FEMTORV32_INTERMISSUM
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`include "PROCESSOR/femtorv32_intermissum.v" // RV32IM with barrel shifter and interrupts
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`endif
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`ifdef NRV_FEMTORV32_GRACILIS
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`include "PROCESSOR/femtorv32_gracilis.v" // RV32IMC with barrel shifter and interrupts
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`endif
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`ifdef NRV_FEMTORV32_PETITBATEAU
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`include "PROCESSOR/femtorv32_petitbateau.v" // under development, RV32IMFC
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`endif
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`ifdef NRV_FEMTORV32_TESTDRIVE
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`include "PROCESSOR/femtorv32_testdrive.v" // CPU under test
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`endif
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/******************************************************************************************************************/
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